(1). Field of the Invention
The invention relates to testability. More specifically, the invention relates to testability of content addressable memory.
(2). Background
Content addressable memory (CAM) addressed caches have gained increasing popularity for use in microprocessor caches. This popularity increase is primarily due to the elimination of the need for a final decode and that such caches permit high set associativity and low power consumption at the expense of some added chip area. Unfortunately, such CAM addressed caches create testing problems because neither the SRAM portion of the array, nor the CAM locations, are directly addressable. In fact, each CAM cell is formed with several transistors, but the only output is a match line indicating match or no match. A match is determined by whether any cell in the row of the match line drives the match line. Thus, CAM testing necessitates developing a scheme whereby only a single column and row are tested at any one time. It may not be possible to develop an algorithmic scheme for such testing and, in any event, such testing would be prohibitively expensive and time consuming for mass marketed components.
In one embodiment, an array of content addressable memory (CAM) cells includes a first plurality of CAM cells and a second plurality of CAM cells. The first plurality of CAM cells is used as a decoder. The second plurality of CAM cells is algorithmically tested on addresses provided by the first plurality of CAM cells.